Intel Ivy Bridge: Everything You Need to Know

Intel is set to roll out its latest generation of processors this spring — destined for super slim notebooks — despite minor setbacks affecting ultra low-voltage models. By normal standards, the launch should mark a new “tick” in the company’s product roadmap, but Intel is going beyond shrinking the current 32nm Sandy Bridge processors by debuting some fundamental advancements with its new 22nm process.

For those unfamiliar, Intel follows a “Tik Tok” model for its processor upgrade cycle. With each “tick” the company moves to a shorter manufacturing process from 32nm to 22nm in this case, dramatically increasing transistor density while increasing the performance and energy efficiency of current microarchitectures. Then, Intel introduces a new processor microarchitecture with an optional “talk” cycle.

Ivy Bridge includes manufacturing and subsystem improvements. It’s a shrinkage of Sandy Bridge and also Intel’s first tri-gate transistor for us, which uses a nonplanar architecture to cram more transistors into less space, therefore consuming less power or the same power envelope. Provides more performance within.

There has been a lot of information about Ivy Bridge since Intel detailed the architecture late last year. We’ll recap some of the key changes and practical implications as well as bringing you up to speed on the latest developments, including the expected launch lineup and specifications.

Tri-gate transistor = better efficiency, performance
Unlike traditional planar transistors, which are flat, Ivy Bridge’s tri-gate transistors use a three-dimensional fin that stands perpendicular to the silicon substrate. It presents many benefits. For starters, Intel can cram more transistors into less space, which will be incredibly valuable as manufacturing technology shrinks to 22nm and beyond.

In addition, when the transistor is in the ‘on’ state, the new design allows for essentially three times the surface area for electrons to travel through, paving the way for improved performance.

Transistors carry an electrical signal while gates control that flow by turning current on and off. Whereas in a typical transistor only the small layer between the channel and the gate is activated when the transistor is turned on, Intel’s tri-gate transistor forms a three-way silicon fin that the gate wraps around, increasing the surface area where the gate actually resides. Electric current flows in. The video below does a better job of explaining it.

This design maximizes transistor switching performance between on and off states and minimizes power waste.

Intel summarizes the practical implications by saying that 22nm 3D tri-gate transistors provide a performance increase of up to 37% at low operating voltages versus Intel’s 32nm planar transistors – a big deal for Atom and ULV chips – or 20% at 1V Closer to high-end desktop and mobile parts.

Alternatively, the new 22nm tri-gate transistors can consume less than half the power at the same performance level as 2D planar transistors on 32nm chips.

Intel also mentioned the possibility of multiple fins standing vertically to the silicon substrate and connected together, as shown on the right, to increase the transistor’s total drive power for higher performance. They haven’t discussed it in detail, but we believe that Intel could use it to more finely tune its 22nm process into higher-end products, or use it as a fail-safe to improve the yield of individual dies. can be used as a method.

The new 22nm tri-gate wafers don’t have to be more expensive to produce. Compared to a hypothetical Intel 22nm planar process, according to Intel’s own estimates, the 3D Tri-Gate process should only add 2-3% to the total cost.

Other architectural changes
Apart from the new transistor design, no major changes have been made to the architecture of Ivy Bridge compared to Sandy Bridge. It continues the 2-chip platform division (CPU + PCH) and is backwards compatible with existing LGA-1155 motherboards, although there will be new chipsets to enable the new features.

In the middle of the die are four x86-64 cores each with 256 KB of dedicated L2 cache and a shared 8 MB L3 cache. On each side of this central part is the system agent and graphics core.

All these components are bound by a ring-bus which transfers data between them. The System Agent has interfaces for a dual-channel DDR3 integrated memory controller, a PCI-Express controller (supporting 16 PCIe 3.0 lanes), a DMI chipset bus, a display controller, and an FDI link for PCH.


But there are some changes here and there as well. First and foremost the graphics core has been completely redesigned and now supports OpenCL 1.1, DirectX 11 and OpenGL 3.1. It will eventually bring Intel integrated GPUs to facilitate parity with AMD.

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